GaN devices are expected to be widely adopted for power switches as production costs are reduced, for example, by fabrication of lateral GaN transistors on lower cost silicon substrates (GaN-on-Si die). Lateral GaN power transistors offer low on-resistance Ron and high current capability per unit active area of the device. To benefit from the inherent performance characteristics of lateral GaN transistors, important design considerations include, for example, device layout (topology), low inductance packaging and effective thermal management.
For larger area lateral switching power transistors capable of switching 20 Amps or more, using conventional device topologies, where large area contact pads are provided around the periphery of the chip, the length of conductive tracks of on-chip metallization becomes very long. The resistance of the on-chip metallization can be comparable to, or even greater than, the Ron of the transistor itself. Furthermore, these long tracks introduce inductance, which significantly degrades the switching performance.
Correspondingly, much energy is wasted, which goes simply to heating or overheating of the track. This tends to put an upper limit on the practical size of such power transistors. PCT International patent application No. PCT/CA2012/000080 entitled “Gallium nitride power devices using island topography”, (GaN Systems Inc.), and related applications, disclose GaN switching devices using Island Technology®. This topology for lateral GaN transistors mitigates this problem by providing the ability to take high current directly on and off the chip to/from each island, thus minimizing the length of the on-chip tracks. That is, contact areas are distributed over the active area of the device. This topology provides a low on resistance (Ron), low inductance, and a compact structure with a gate width double that of a conventional multi-finger design of a similar device size, with superior current handling per unit area. A breakdown voltage exceeding 1200V can be achieved.
Another large area, multi-island, transistor structure is disclosed in PCT International application No. PCT/CA2014/000762 and U.S. patent application Ser. No. 14/568,507, each entitled “Fault Tolerant Design for Large Area Nitride Semiconductor Devices” (GaN Systems Inc.), which claim priority from U.S. Provisional Patent application No. 61/896,871, filed 29 Oct. 2013. These patent applications disclose redundant-cell, yield enhancement techniques, providing a practical approach, which allows for manufacturing of larger dies. For example, large gate width devices may be fabricated having a current switching capability in excess of 100 A.
To take advantage of these novel structures and other large area, lateral GaN power devices for high voltage/high current applications, improved interconnect and packaging schemes are required. Packaging solutions are required that offer both low inductance interconnections and effective thermal management.
Packaging solutions currently used for power devices typically comprise one of two main types of structures. Firstly, there are a number of industry standard power modules for packaging one or more power devices that are based on conventional wirebond solutions for bare die. For example, the back-side (substrate) of a semiconductor die comprising a power transistor is mounted on a thermal substrate of a power module, using conventional back-side die-attach techniques, soldering or sintering. Then, source, drain and gate connections between the contact pad areas on the front-side of the die and the metal contact areas of the packaging module are then made by conventional wirebonding. External connections of the packaging module may comprise various standard arrangements of pins or leads.
Alternatively, there are many variants of PQFN (Power Quad Flat No Lead) type packages. These packages typically comprise organic or ceramic substrates, which provide external metal contact pads, e.g. copper lands, instead of leads or pins. For packaging of vertical power devices, where source or drain contacts may be provided on the back-side of the GaN die, PQFN packages provide a copper die pad and may use wirebonds, copper clips, or flip-chip on leadframe interconnections. For example, some PQFN packages use a copper clip to hold the power transistor die in place and provide thermal contact with a thermal substrate.
For lateral GaN power devices, some known drawbacks of these existing packaging solutions include, e.g.:                a conventional PQFN package for vertical power transistors provides a back-side source connection, and front-side drain and gate connections, whereas for lateral GaN power transistors, all electrical connections, i.e. source, drain and gate contact areas are made to the front-side (top) of the GaN die;        such PQFN packages are not configured to provide a ground connection between a front-side source contact and the die substrate/thermal pad within the package;        for lateral GaN power transistors, electrical issues of wirebonding include insufficient current handling and excessive inductance of the long thin lengths of wirebonds;        wirebonding solutions may require many layers of wirebonds and take up significant space, i.e. tend to be large in the vertical dimension (tall/thick/high profile), which places physical limitations on the design of power modules;        there is a significant mismatch of CTE (Coefficient of Thermal Expansion) between a GaN-on-Si die and the copper die pad of standard PQFN package or the ceramic substrate of a power module;        the copper die pad of a standard PQFN package adds extra thermal resistance compared to a bare die on a ceramic substrate of a conventional wirebonded power module.        
Thus, there is a need for alternative packaging solutions and/or improvements that provide for one or more of increased current handling, reduced inductance, improved thermal management, and a lower profile package, which can be manufactured at a cost that is similar to, or lower than, existing packaging solutions.
In particular, there is a need for alternative or improved packaging schemes for nitride power semiconductor devices, such as GaN power transistors and for systems comprising one or more lateral GaN power transistors.